Memory system segmented power supply and control
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United States of America Patent
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Aug 1, 2006
Grant Date -
Jul 7, 2005
app pub date -
Dec 29, 2003
filing date -
Dec 29, 2003
priority date (Note) -
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Abstract
A memory device having memory cells supplied with a separate higher voltage power than the separate power supplied to memory logic, and a lower power state that entails removing power from at least some of the logic such that refresh operations to preserve the contents of the memory cells continue to take place, but at least some of the interface to the memory device is powered down to reduce power consumption.
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