Managing a secure environment using a chipset in isolated execution mode
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United States of America Patent
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Aug 1, 2006
Issued Date -
N/A
app pub date -
Sep 22, 2000
filing date -
Mar 31, 2000
priority date (Note) -
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Abstract
A chipset is initialized in a secure environment for an isolated execution mode by an initialization storage. The secure environment has a plurality of executive entities and is associated with an isolated memory area accessible by at least one processor. The at least one processor has a plurality of threads and operates in one of a normal execution mode and the isolated execution mode. The executive entities include a processor executive (PE) handler. PE handler data corresponding to the PE handler are stored in a PE handler storage. The PE handler data include a PE handler image to be loaded into the isolated memory area after the chipset is initialized. The loaded PE handler image corresponds to the PE handler.
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