Multichip wafer level packages and computing systems incorporating same

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7087992
SERIAL NO

10999435

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Abstract

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The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

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Patent Owner(s)

Patent OwnerAddress
U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT100 WALL STREET SUITE 1600 NEW YORK NY 10005

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Boon, Suan Jeung Singapore, SG 58 1447
Chia, Yong Poo Singapore, SG 63 1318
Chua, Swee Kwang Singapore, SG 29 777
Eng, Meow Koon Singapore, SG 35 822
Huang, Suangwu Singapore, SG 8 232
Low, Siu Waf Singapore, SG 30 1223
Neo, Yong Loo Singapore, SG 23 611
Zhou, Wei Singapore, SG 770 4458

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