Shared cache wordline decoder for redundant and regular addresses
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United States of America Patent
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Aug 8, 2006
Grant Date -
N/A
app pub date -
Mar 22, 2000
filing date -
Mar 22, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
In one embodiment, a wordline decoder provides access to cache memory locations when addresses are bypassed directly from arithmetic circuitry in redundant form. The wordline decoder is also designed to provide access to cache memory locations when addresses are received from registers in an unsigned binary form. The combined functionality is provided in a pre-decode circuit by selectively replacing one of a plurality of redundant bit vectors with a constant bit vector when redundant addressing is not enabled.
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