Managing multiple processor performance states
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United States of America Patent
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Aug 8, 2006
Grant Date -
Jun 26, 2003
app pub date -
Dec 21, 2001
filing date -
Dec 21, 2001
priority date (Note) -
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Abstract
In one embodiment of the invention, a performance information associated with a processor is read. A processor performance table that corresponds to the performance information is located. The performance table includes a plurality of performance parameters to control performance of the processor. A performance state (PS) structure is updated using one of the processor performance table and a default table.
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