Method and apparatus for testing a circuit using a die frame logic analyzer
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United States of America Patent
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Aug 8, 2006
Grant Date -
Oct 2, 2003
app pub date -
Mar 29, 2002
filing date -
Mar 29, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A die frame logic analyzer unit. For one aspect, a programmable logic analyzer unit is provided, wherein at least a first portion of the programmable logic analyzer unit is provided in a die frame. The programmable logic analyzer unit is to test a function of an integrated circuit on a wafer that includes the die frame.
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