Threshold voltage (Vth), power supply (VDD), and temperature compensation bias circuit for CMOS passive mixer
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United States of America Patent
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Aug 15, 2006
Grant Date -
Sep 30, 2004
app pub date -
Mar 31, 2003
filing date -
Mar 31, 2003
priority date (Note) -
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Abstract
A biasing circuit for a CMOS passive mixer core to stabilize its conversion gain, linearity and noise figure. The RF inputs are fed differentially from the two RF ports, the LO inputs are fed differentially from the two LO ports, and the IF outputs are obtained at the two IF ports. The biasing circuit comprises a reference current derived from the bandgap voltage and a n-channel MOSFET transistor. The conversion gain is stabilized by keeping the Vgs-Vth value of the passive mixer core almost constant at all process corners, temperature and power supply changes. This is achieved by implementing Vs in such a way that it will increase the same amount as VDD decreases, and that Vs will decrease the same amount as Vth increases.
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