Random access memory controller with out of order execution
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United States of America Patent
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Aug 15, 2006
Grant Date -
Feb 13, 2003
app pub date -
Aug 9, 2002
filing date -
Aug 9, 2001
priority date (Note) -
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Abstract
A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge in an order that can be different from the order of the corresponding client transactions. The command scheduler may also re-order memory access commands such as read and write. The slicing and out-of-order command scheduling allow a reduction in memory latency. The data transfer to and from clients can be kept in order.
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