Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM
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United States of America Patent
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Aug 22, 2006
Grant Date -
Aug 11, 2005
app pub date -
Dec 23, 2004
filing date -
Dec 25, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.
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