Method, system, and apparatus for reducing power consumption of a memory

United States of America Patent

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Sep 5, 2006
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Oct 9, 2003
app pub date
Apr 9, 2002
filing date
Apr 9, 2002

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Abstract

A method, system, and apparatus to reduce power consumption of a memory by actively asserting the CKE pin based at least in part on a LRU status of the rows in an active mode.

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Patent Owner	Address
INTEL CORPORATION	2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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G06F:ELECTRIC DIGITAL DATA PROCESSING

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Inventor Name	Address	# of filed Patents	Total Citations
Saxena, Alankar	Folsom, CA	8	357
Sreenivas, Aditya	Eldorado Hills, CA	41	1096

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Method, system, and apparatus for reducing power consumption of a memory

Number of patents in Portfolio can not be more than 2000

United States of America Patent

10119864

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PATENT NO	7103730
APP PUB NO	20030191915A1
SERIAL NO	10119864
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
September 05, 2006	US,7103730,B2 US7103730B2	GRANTED PATENT AS SECOND PUBLICATION
October 09, 2003	US,20030191915,A1 US20030191915A1	FIRST PUBLISHED PATENT APPLICATION

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10119864

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