Self-aligned trench DMOS transistor structure and its manufacturing methods

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United States of America Patent

PATENT NO 7109552
SERIAL NO

10976865

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Abstract

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A self-aligned trench DMOS transistor structure of the present invention comprises a self-aligned source structure and a self-aligned trench gate structure, in which the self-aligned source structure comprises a p-base diffusion region, a self-aligned n.sup.+ source diffusion ring, a self-aligned p.sup.+ contact diffusion region, and a self-aligned source contact window; the self-aligned trench gate structure comprises a self-aligned silicided conductive gate structure, a self-aligned polycided conductive gate structure or a self-aligned polycided trenched conductive gate structure. The self-aligned trench DMOS transistor structure as described is fabricated by using only one masking photoresist step and can be easily scaled down to obtain a high-density trench DMOS power transistor with ultra low on-resistance, low gate-interconnection parasitic resistance, and high device ruggedness.

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Patent Owner(s)

Patent OwnerAddress
SILICON-BASED TECHNOLOGY CORP1F NO 23 R&D RD 1 SCIENCE-BASED INDUSTRIAL PARK HSINCHU R O C

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Wu, Ching-Yuan Hsinchu, TW 57 975

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