Importance

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Abstract

A content addressable memory includes a priority encoder that is in communication with an array of the content addressable memory cells to receive match signals, and from the match signals generating an output index signal in accordance with a priority sequence of the match signals. The priority encoder has a plurality of input circuits to receive the match signals from the CAM array. A priority setting circuit receives a priority transformation signal indicating a priority index for modification of the priority sequence. An encoding circuit is in communication with the plurality of input circuits and the priority setting circuit for generating the output index signal in accordance with the priority sequence. The priority encoder circuit further includes an enabling circuit for receiving an enabling signal. The enabling circuit communicates the enabling signals to the encoding circuit, such that upon deactivation of the enabling signal, the encoding circuit generates the output signal in accordance with the priority sequence with no modification by the priority setting circuit. The priority index indicates a region of the content addressable memory exempted from effective comparison. This allows the CAM array to be searched for multiple matches of the comparand. The priority index thus is an index address of the content addressable memory determined with a previous search of the content addressable memory. The priority index is provided to the priority setting circuit through a word line decoder of the array of content addressable memory cells.

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