Circuits and methods for testing programmable logic devices using lookup tables and carry chains
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 19, 2006
Grant Date -
N/A
app pub date -
Oct 9, 2002
filing date -
Oct 9, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Circuit implementations and test methods enable the testing of lookup table (LUT) input paths, 'stuck at' memory cell values, and carry chains. One method includes storing a first bit pattern in each LUT, configuring the carry chain to perform a wide AND function of the LUT outputs, and cycling the inputs of each LUT while comparing the carry chain output to an expected value and reporting the PLD faulty if a difference is detected. The carry chain is configured to perform a wide OR function, and the cycling step is repeated. The bit pattern within each LUT is changed to the complement of the first bit pattern by providing a series of shift commands or by otherwise storing new values in the LUT, and the configuring and cycling steps are repeated. The invention also provides PLD circuit implementations that can be used to perform the described methods.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully