Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC)
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United States of America Patent
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Sep 19, 2006
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N/A
app pub date -
Feb 28, 2002
filing date -
Feb 28, 2002
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Abstract
A flexible architecture for nesting joint test action group (JTAG) test access port (TAP) controllers for FPGA-based embedded system-on-chip (SoC) is provided. Advantageously, a programmable approach permits bits in a selectable bit register (302) to be selected based on the number of JTAG TAPs that will be utilized. The selected bits can be used to vary the apparent length of an instruction register (302). Importantly, the flexible architecture permits access to any combination of a plurality of JTAG TAP controllers in the FPGA-based embedded SoC without the need to rewire any I/O pins of the FPGA and/or embedded IP cores.
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