Capacitance multiplier circuit exhibiting improving bandwidth
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 26, 2006
Grant Date -
Apr 27, 2006
app pub date -
Oct 25, 2004
filing date -
Oct 25, 2004
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A monolithic capacitance multiplication circuit serves to reduce the required die area when larger capacitance values are needed such as in filter and loop frequency compensation circuits. A current mirror/cascoding device arrangement reduces the effective series resistance of the multiplier capacitor. As a result, the multiplier topology exhibits improved bandwidth over prior art capacitance multiplier circuits.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully