Method and apparatus for decomposing a design layout

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United States of America Patent

PATENT NO 7114141
SERIAL NO

10222088

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Abstract

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Some embodiments of the invention provide a method of decomposing a design layout. The method decomposes the layout into a tessellated graph with several edges. It then computes the capacity of the edges based on a interconnect line model that is used to connect elements in the design layout. The layout has two orthogonal coordinate axes. At least one interconnect line specified by the model is neither parallel nor perpendicular to the coordinate axes. Also, in some embodiments, some of the edges are neither parallel nor perpendicular to the coordinate axes.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC A CORP OF DELAWARE2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Caldwell, Andrew Santa Clara, CA 120 1490
Teig, Steven Menlo Park, CA 333 6577

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