Nonvolatile semiconductor memory and method of manufacturing the same
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United States of America Patent
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Oct 3, 2006
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N/A
app pub date -
Jun 14, 2004
filing date -
Mar 28, 2000
priority date (Note) -
Expired
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Abstract
A trench region 14 is formed in a memory cell P-type well 13. Two NAND-type memory cell units ND1 and ND2 are respectively formed along both side wall portions of this trench region 14. A floating gate FG and a control gate CG in these NAND-type memory cell units ND1 and ND2 are formed self-aligningly without using memory cell units ND1 and ND2 is formed via an interlayer dielectric 30. The bit line pitch of this bit line BL is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.
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