Debug port disable mechanism
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United States of America Patent
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Oct 3, 2006
Issued Date -
N/A
app pub date -
Dec 20, 2002
filing date -
Feb 13, 2002
priority date (Note) -
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Abstract
A circuit generally comprising a debug port and a processor is disclosed. The processor may be configured to (i) bootstrap to a first memory, (ii) disable said debug port while in a first mode of at least three modes, (iii) authenticate said debug port while in a second mode of said modes and (iv) disable said debug port in response to failing said authentication.
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