Variably controlled delay line for read data capture timing window
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United States of America Patent
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Oct 3, 2006
Grant Date -
Dec 4, 2003
app pub date -
May 30, 2002
filing date -
May 30, 2002
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Disclosed is a method and circuit for variably controlling a delay line for a read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.
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