System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocks
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United States of America Patent
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Oct 3, 2006
Issued Date -
N/A
app pub date -
Jul 16, 2004
filing date -
Mar 3, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock.
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