Method and an apparatus to generate static logic level output
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United States of America Patent
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Oct 24, 2006
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app pub date -
Dec 14, 2004
filing date -
Dec 17, 2003
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Abstract
A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The apparatus may further include a second circuit coupled to the first circuit to drive the first circuit. The second circuit may comprise at least one of a latch and a feedback device.
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