Interlocking memory/logic cell layout and method of manufacture
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 24, 2006
Issued Date -
N/A
app pub date -
Mar 24, 2005
filing date -
Mar 26, 2004
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully