Method for entering circuit test mode
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United States of America Patent
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Oct 24, 2006
Issued Date -
N/A
app pub date -
Oct 5, 2001
filing date -
Oct 26, 2000
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A method for entering test mode of an integrated circuit device is disclosed. In one embodiment of the present invention, after a lockout period, a test controller generates a signal indicating the integrated circuit is willing to enter the test mode. After the signal, the test controller monitors a test interface during a predetermined period of time for a digital password. Then, in response to a valid password being received within the predetermined period, the test controller enters the test mode. In another embodiment, in addition to the above steps, in response to the valid password being received, the test controller generates an acknowledge signal. In one embodiment, the predetermined period of time takes place during a holdoff period after the lockout period. In another embodiment, the test interface is serial.
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