Layout technique for C3MOS inductive broadbanding
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United States of America Patent
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Nov 7, 2006
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N/A
app pub date -
May 18, 2004
filing date -
May 17, 2001
priority date (Note) -
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Abstract
An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and aligns the edges of the resistor, inductor, and transistor regions near the common edge of adjacent cells to decrease the length of the cell-to-cell interconnect lines.
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