Scheduling system using packet FIFOs and cell FIFOs for converting IP packets to ATM cells
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United States of America Patent
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Nov 7, 2006
Grant Date -
Nov 29, 2001
app pub date -
May 25, 2001
filing date -
May 25, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A scheduling circuit of the present invention includes an IP (Internet Protocol) scheduling/format converting section for scheduling input IP packets and converting each of them to ATM (Asynchronous Transfer Mode) cells. The IP scheduling/format converting section includes a plurality of packet FIFOs (First-In First-Out memories). The ATM cells output from each packet FIFO are written to corresponding one of a plurality of cell FIFOs. An ATM scheduling section schedules the ATM cells received from each cell FIFO cell by cell.
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