Active memory processing array topography and method
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United States of America Patent
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Nov 7, 2006
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N/A
app pub date -
Jul 28, 2003
filing date -
Mar 31, 2003
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Abstract
An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements. The processing elements are logically arranged in a plurality of logical rows and logical columns. The array is logically folded to minimize the length of the longest path between processing elements by physically interleaving the processing elements so that the processing elements in different logical rows a physically interleaved with each other and the processing elements in different logical columns a physically interleaved with each other.
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