Phase jumping locked loop circuit
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United States of America Patent
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Nov 14, 2006
Issued Date -
N/A
app pub date -
Feb 25, 2003
filing date -
Sep 3, 2002
priority date (Note) -
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Abstract
A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.
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