Parallel computation processor, parallel computation control method and program thereof
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United States of America Patent
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Nov 14, 2006
Grant Date -
Apr 3, 2003
app pub date -
Sep 26, 2002
filing date -
Oct 1, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A parallel computation processor being capable of high-speed loop operation. When instruction decoders decode the VLOOP instruction, which triggers loop operation, an instruction buffer starts storing normal instructions. The instruction buffer dispatches a VLIW instruction composed of n pieces of normal instructions to execution units each time n pieces of instructions are stored therein. The execution units concurrently execute the instructions. After all instructions comprised in a loop have been stored in the buffer and once dispatched as VLIW instructions to be executed, the loop is executed repeatedly.
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