Assertion checking using two or more cores
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United States of America Patent
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Nov 14, 2006
Issued Date -
N/A
app pub date -
Oct 1, 2004
filing date -
Jul 6, 2004
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Abstract
An SoCs with functionally reconfigurable modules employing the modules to configure circuitry for performing assertion checking. Both at-speed assertion checking as well as continuous single step (CSS) assertion checking is disclosed. Advantageously, the checking of the various cores within the SoC is carried out concurrently, in subsets of the entire set of assertions that need to be checked out. Advantageously, bit extraction and injection is used in CSS assertion checking to permit use of relatively small registers for the assertion checking of each subset of assertions.
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