Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 21, 2006
Issued Date -
N/A
app pub date -
Aug 19, 2003
filing date -
Sep 18, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A disclosed semiconductor memory device includes multilevel memory cells in which data in the cells is arranged according to a coding method that allows error correction. One disclosed device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2.sup.n levels of data, each expressed by n (n.gtoreq.2) number of bits (X1, X2, Xn). When an input logical address is converted into a physical address, a determination is made whether the logical address space matches the physical address space. If there is not a match, the most significant bit X1 is specified once using a reference value, and the specified bit is output from one of the cells corresponding to the physical address. If there is not match, the bits (X2, . . . , Xn) are specified by an n--time specifying operation using maximum n number of different reference values.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully