Method and apparatus for pre-computing routes

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United States of America Patent

PATENT NO 7139994
APP PUB NO 20030088844A1
SERIAL NO

10041957

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Abstract

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Some embodiments provide a method of pre-computing routes for nets in a region of an integrated circuit ('IC') layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. For a particular set of potential sub-regions, the method then identifies a set of routes that traverse the particular set of potential sub-regions, where at least one of the identified routes has at least one diagonal edge. The method then stores the identified routes.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE BUILDING 5 SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chao, Heng-Yi San Jose, CA 5 64
Ganley, Joseph L Vienna, VA 23 383
Teig, Steven Menlo Park, CA 333 6577

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