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United States of America Patent

PATENT NO 7141819
APP PUB NO 20040232548A1
SERIAL NO

10798567

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A semiconductor package 11 which has a plurality of connection terminals 14 to be connected to a board and a plurality of test terminals 15, which usually do not need to be connected to the board and are for performance test by the maker, on a joint surface 12 thereof to the board. Placed in the semiconductor package are a predetermined-pitch area 16 where the connection terminals 14 are arranged at predetermined pitches in a lattice and a narrow-pitch area 17 where the test terminals 15 are arranged at pitches narrower than the predetermined pitches in a lattice.

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Patent Owner(s)

Patent OwnerAddress
LAPIS SEMICONDUCTOR CO LTDKANAGAWA COUNTY YOKOHAMA JAPAN

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Maruko, Toguto Tokyo, JP 1 14

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