Digital delay device, digital oscillator clock signal generator and memory interface
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United States of America Patent
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Dec 12, 2006
Grant Date -
May 19, 2005
app pub date -
Oct 1, 2004
filing date -
Oct 1, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.
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