Apparatus, method and limited set of messages to transmit data between scheduler and a network processor
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United States of America Patent
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Dec 12, 2006
Grant Date -
Nov 28, 2002
app pub date -
Mar 12, 2002
filing date -
Mar 21, 2001
priority date (Note) -
Expired
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Abstract
An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request.
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