Importance

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Abstract

An integrated circuit, such as a programmable logic device, implements a single bit transition counter in logic. The counter preferably comprises a first stage receiving a clock signal having a first clock rate and generating a least significant bit in a count. A plurality of intermediate stages are coupled to the first stage, where each intermediate stage receives an output from the immediate previous stage and an inverted output of each other previous intermediate stage, and generates a next most significant bit in a count. Finally, a last stage of the counter receives an inverted output of each previous intermediate stage except the immediate intermediate previous stage and generating a most significant bit in a count.

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First Claim