Method and apparatus for adjusting the performance of a synchronous memory system

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United States of America Patent

PATENT NO 7149856
SERIAL NO

10386210

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Abstract

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A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INCSAN JOSE CA

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Barth, Richard M Palo Alto, CA 112 4752
Chau, Pak Shing San Jose, CA 38 1502
Davis, Paul G San Jose, CA 59 1955
Donnelly, Kevin S San Fransisco, CA 95 4696
Garlepp, Bruno Werner Mountain View, CA 9 343
Portmann, Clemenz Cupertino, CA 17 247
Sidiropoulos, Stefanos Stanford, CA 96 3728
Stark, Donald C Los Altos, CA 102 3489
Tsern, Ely K Los Altos, CA 168 5566

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