Power management for an integrated graphics device
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United States of America Patent
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Dec 12, 2006
Issued Date -
N/A
app pub date -
May 9, 2002
filing date -
May 9, 2002
priority date (Note) -
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Abstract
In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
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