Demultiplexer circuit
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United States of America Patent
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-
Dec 19, 2006
Grant Date -
Jan 23, 2003
app pub date -
Jul 17, 2002
filing date -
Jul 18, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A demultiplexer circuit which can simultaneously demultiplex plural pieces of input data while minimizing the circuit scale. The demultiplexer circuit includes an input line identification information addition circuit 2 for giving input line identification information to input data which have data identification information and are inputted through plural input lines 1, respectively; a multiplexer 4 for outputting the input data which have been given the input line identification information, respectively, by the input line identification information addition circuit 2 through one common line 5; a filter 6 for filtering the data outputted from the multiplexer 4 on the basis of the input line identification information and the data identification information at one time; and a filter table 7 that contains filtering conditions which are used in the filter 6.
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