Method and apparatus to enhance processor power management
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United States of America Patent
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Dec 26, 2006
Grant Date -
Jun 27, 2002
app pub date -
Nov 26, 2001
filing date -
Sep 30, 2000
priority date (Note) -
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Abstract
A method and an apparatus to dynamically transition a processor between two performance states, high performance and low power. Predetermined core clock frequency and supply voltage levels of the processor define each performance state. Transitioning the supply voltage while the processor is in the active mode and transitioning the frequency while the processor is in the sleep mode significantly reduce the processor latency.
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