Coaxial through chip connection
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United States of America Patent
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Jan 2, 2007
Issued Date -
N/A
app pub date -
Jan 10, 2006
filing date -
Jun 14, 2005
priority date (Note) -
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Abstract
A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing the annulus trench with a metal, etching a via trench within the periphery of the annulus trench, making a length of the via trench electrically conductive, and thinning the substrate to expose the metal and the electrically conductive material.
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