System and method for reading data stored in a semiconductor device having multilevel memory cells
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United States of America Patent
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Jan 2, 2007
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N/A
app pub date -
Aug 19, 2003
filing date -
Sep 18, 1996
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Abstract
A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. The multilevel memory cells are arranged so as to correspond to a physical address space, each cell storing 2.sup.n levels of data each expressed by n (n.gtoreq.2) number of bits (X1, X2, . . . , Xn). A logical address is converted into a physical address of the physical address space. A judgement is made as to whether a logical address space including the logical address matches the physical address space. When matched, the most significant bit X1 is specified by performing a single comparison operation using a reference value. The specified bit is output from one of the cells corresponding to the physical address. If not matched, the bits (X2, . . . , Xn) are specified by performing multiple comparison operations using different reference values.
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