Solderless electronics packaging and methods of manufacture
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United States of America Patent
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Jan 9, 2007
Issued Date -
N/A
app pub date -
Nov 30, 2004
filing date -
Nov 30, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive particles, and a thin, flexible apertured support that aligns the particles with corresponding lands on the IC package and substrate. A compression connector may also be used to electrically couple an IC to an IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.
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