Memory management system having a linked list processor

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United States of America Patent

PATENT NO 7162551
APP PUB NO 20050111353A1
SERIAL NO

10699315

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Abstract

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A memory management system adapted to process linked list data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of linked list files by the memories. The head and tail buffers and at any intermediate buffers of a linked list are written into the high speed memories. The intermediate buffers are immediately transferred from the high speed memories to said bulk memory while leaving the head buffer and the tail buffer of the linked list in the high speed memories. In read operations, the head and tail buffers are read from the high speed memories. The intermediate buffers are transferred from the bulk memory to said the high speed memory and then read from the high speed memories.

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Patent Owner(s)

Patent OwnerAddress
WSOU INVESTMENTS LLC11150 SANTA MONICA BLVD SUITE 1400 LOS ANGELES CA 90025

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Zievers, Peter J Naperville, IL 14 153

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