Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration
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United States of America Patent
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Jan 9, 2007
Issued Date -
N/A
app pub date -
Feb 21, 2001
filing date -
Feb 21, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one parameter. The virtual instruction expansion store includes at least one instruction template and at least one parameter selector. The substitution logic forms a sequence of at least one expanded instruction. In a example, the substitution logic sign-extends the at least one parameter to form an immediate value of the at least one expanded instruction in a manner specified by the at least one parameter selector. In another example, the substitution logic concatenates a first parameter and a second parameter of the virtual instruction to form an immediate value of the at least one expanded instruction in a manner specified by the at lest one parameter selector.
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