Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device
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United States of America Patent
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Jan 16, 2007
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app pub date -
May 6, 2003
filing date -
May 6, 2003
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Abstract
The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.
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