US Patent No: 7,165,164
Number of patents in Portfolio can not be more than 2000
Method and apparatus including heuristic for sharing TLB entries
Stats
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Jan 16, 2007
Issued date -
Sep 24, 2003
filing date -
10/670,637
serial no -
In Force
status
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Abstract
A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Sharability of virtual address translations by logical processors may be determined by comparing page table physical base addresses of the logic processors. Using the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,335,333 Guess mechanism for faster address calculation in a pipelined microprocessor | 27 | 1991 | |
| 5,640,533 Translation lookaside buffer (TLB) arrangement wherein the TLB contents are retained from task when it is swapped out and reloaded when the task is rescheduled | 14 | 1995 | |
| 5,940,872 Software and hardware-managed translation lookaside buffer | 38 | 1996 | |
| 6,138,225 Address translation system having first and second translation look aside buffers | 15 | 1997 | |
| 6,728,858 Method and apparatus including heuristic for sharing TLB entries | 8 | 2001 | |
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| 4,797,814 Variable address mode cache | 111 | 1986 | |
| 4,779,188 Selective guest system purge control | 86 | 1987 | |
| 5,317,705 Apparatus and method for TLB purge reduction in a multi-level machine system | 124 | 1993 | |
| 6,289,432 Sharing segments of storage by enabling the sharing of page tables | 9 | 1998 | |
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| 4,812,969 Address translation unit | 20 | 1986 | |
| 5,437,016 Apparatus and method for translating logical addresses for virtual machines | 14 | 1992 | |
| 6,138,226 Logical cache memory storing logical and physical address information for resolving synonym problems | 14 | 1999 | |
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| 6,260,131 Method and apparatus for TLB memory ordering | 32 | 1998 | |
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| 6,598,050 Apparatus and method for limited data sharing in a multi-tasking system | 4 | 2000 | |
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| 6,085,296 Sharing memory pages and page tables among computer processes | 143 | 1997 | |
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| 6,564,311 Apparatus for translation between virtual and physical addresses using a virtual page number, a physical page number, a process identifier and a global bit | 10 | 2000 | |
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| 5,893,166 Addressing method and system for sharing a large memory address space using a system space global memory section | 21 | 1997 | |
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| 6,105,113 System and method for maintaining translation look-aside buffer (TLB) consistency | 44 | 1997 | |
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| 5,754,818 Architecture and method for sharing TLB entries through process IDS | 38 | 1996 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 16, 2014 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 16, 2018 |
| Fee | Large entity fee | small entity fee | micro entity fee |
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| Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |