US Patent No: 7,169,662

Number of patents in Portfolio can not be more than 2000

Methods for making semiconductor structures having high-speed areas and high-density areas

Stats

ATTORNEY / AGENT: (SPONSORED)
 

Importance

Loading Importance Indicators... loading....

Abstract

Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a metallization layer simultaneously into the high-density area and the high-speed area. The metallization layer includes a combination of substances and compounds that reduce vertical resistance, reduce horizontal resistance, and inhibit cross-diffusion.

Loading the Abstract Image... loading....

First Claim

Related Publications

Loading Related Publications... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
MICRON TECHNOLOGY, INC.BOISE, ID18720

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cho, Chih-Chen Taipei, TW 109 1615
Wang, Zhongze Boise, ID 76 440

Cited Art

Patent Info (Count) # Cites Year
 
LUCENT TECHNOLOGIES INC. (2)
6,174,807 Method of controlling gate dopant penetration and diffusion in a semiconductor device 9 1999
6,274,409 Method for making a semiconductor device 16 2000
 
UNITED MICROELECTRONICS CORP. (2)
5,899,742 Manufacturing method for self-aligned local interconnects and contacts simultaneously 56 1998
6,083,828 Method for forming a self-aligned contact 23 1999
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
6,121,129 Method of contact structure formation 12 1997
 
KABUSHIKI KAISHA TOSHIBA (1)
6,300,178 Semiconductor device with self-aligned contact and manufacturing method thereof 11 1998
 
MICRON TECHNOLOGY, INC. (1)
6,730,553 Methods for making semiconductor structures having high-speed areas and high-density areas 7 2001
 
RENESAS ELECTRONICS CORPORATION (1)
6,069,038 Method of manufacturing a semiconductor integrated circuit device 25 1999
 
SAMSUNG ELECTRONICS CO., LTD. (1)
6,451,708 Method of forming contact holes in a semiconductor device 18 2000
 
SPANSION LLC (1)
6,271,087 Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects 33 2000
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
5,843,816 Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell 17 1997

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (3)
7,829,991 Stackable ceramic FBGA for high thermal applications 2 2007
8,072,082 Pre-encapsulated cavity interposer 1 2008
8,399,297 Methods of forming and assembling pre-encapsulated assemblies and of forming associated semiconductor device packages 0 2011
 
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. (1)
7,670,946 Methods to eliminate contact plug sidewall slit 1 2006

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
7.5 Year Payment $3600.00 $1800.00 $900.00 Jul 30, 2014
11.5 Year Payment $7400.00 $3700.00 $1850.00 Jul 30, 2018
Fee Large entity fee small entity fee micro entity fee
Surcharge - 7.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00