Expansion constrained die stack
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United States of America Patent
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Feb 6, 2007
Grant Date -
Mar 17, 2005
app pub date -
Aug 30, 2004
filing date -
Aug 29, 2003
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Structures and techniques for mounting semiconductor dies are disclosed. In one embodiment, the invention includes a stack of printed wiring board assemblies that are connected via interconnection components. At least one of the printed wiring board assemblies includes an interposer substrate having a constraining layer that includes carbon.
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