Recovery of a serial bitstream clock at a receiver in serial-over-packet transport
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United States of America Patent
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Feb 13, 2007
Grant Date -
N/A
app pub date -
Dec 13, 2004
filing date -
Dec 13, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
A receiver for recovering a serial clock of a transmitter is provided. The receiver comprises a buffer configured to store packets received from the transmitter. The packets may be sent through a packet switched network that may incur packet delay during transmission through the network. A memory controller is configured to determine a fill level of the buffer. A frequency generator is configured to generate a clock frequency, where the frequency is used to determine when to read packets from the buffer. A frequency controller is configured to instantaneously adjust the frequency of the frequency generator based on an algorithm that determines the clock frequency based on the fill level of the buffer. Accordingly, by adjusting the frequency outputted by the frequency generator, the frequency controller is able to recover the serial clock of the transmitter.
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