Method and system for cache power reduction

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United States of America Patent

PATENT NO 7177981
APP PUB NO 20040225839A1
SERIAL NO

10434617

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Abstract

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A method and system is disclosed for minimizing data array accesses during a read operation in a cache memory. The cache memory has one or more tag arrays and one or more data arrays. After accessing each tag array, a selected data array is identified, and subsequently activated. At least one predetermined data entry from the activated data array is accessed, wherein all other data arrays are deactivated during the read operation. In another example, the cache memory is divided into multiple sub-groups so that only a particular sub-group is involved in a memory read operation. By deactivating any many circuits as possible throughout the read operation, the power consumption of the cache memory is greatly reduced.

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Patent Owner(s)

Patent OwnerAddress
VIA-CYRIX INC2703 NORTH CENTRAL EXPRESSWAY RICHARDSON TX 75080

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Davis, Timothy D Arlington, TX 18 576

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